This paper describes pipelined switched-current A/D converter designed in 0.6 µm BiCMOS technology. Modified conventional-restoring algorithm, called redundant-sign-digit (RSD), was implemented what decreases the amount of high-precision components. Two modes of operation are possible. By changing from pipeline conversion to cycling mode, less power dissipation is obtained at the expense of conversion time. Proposed A/D converter is suitable for conversion of the current with very low amplitude from analog into digital domain. Current mode enables operation down to 3 V thus is suitable for battery powered applications. The system integrates band-gap reference and independent supervisory circuit with 1% accuracy. Current consumption in sleep mode is less than 1 mA. A/D converter is prepared to meet 1452.2 specifications.

This work is an overview of recently proposed methods on combining DACs in order to improve performance. Some further development of these techniques are also presented. The techniques aim at reducing glitches and sensitivity towards limited output impedance in current sources.

This paper investigates the effects of Integral Non-Linearity (INL) on the performances of both A/D converters and Digital Communication Systems, which exploit Direct Digital Modulation. The performances of both PCM and Sigma-Delta converters affected by INL are considered and compared. Then, the effects of INL upon the BER performances of an OFDM system are evaluated and modeled. The accuracy of the theoretical model is discussed with respect to the ADC resolution and INL levels. It is shown that a multibit Sigma-Delta converter, operating at a low oversampling ratio, may outperform PCM converters.

A fully digital algorithm is described for acquiring and correcting the errors of the feedback DAC used in a multibit ΔΣ MASH ADC. The method operates in the background and is highly accurate. It is particularly useful for wideband ADCs, where mismatch error shaping becomes ineffective. Combined with an improved digital adaptive compensation technique, which greatly reduces the raw quantization leakage in MASH architecture, it makes the design of fast and accurate ADCs using inaccurate components possible.

This paper presents an improved rnethod to digitally correct for statit, analog circuit imnperfections in a two-stage, 6^th order, cascaded (6-3) sigma-delta modulator. By adding a digital correction term to the output of die digital noise cancellation filter, the first stage parasitic quantization noise due to finite amplifier gain and C-Ratio mismatches can be completely removed. A 6-3 modulator implemented as a fully differential switched-capacitor circuit, designed for an OSR of 16, has heen fabricated in a 1.2 µm double-poly n-well CMOS process. Improvements have been made in the null cancellation leading to approximately a 10 dB increase in SNDR ovor a range of signal amplitudes from 12 µVolts to 500 mV. A peak SNDR/SFDR of 87/100 dB for a 1 MHz sample rate and 84/93 dB for a 2.5 MHz sample rate have heen achieved.