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J. J. Ocampo-Hidalgo, A. Garcia-Ortiz, L. D. Kabulepa, M. Glesner
A Reconfigurable Sigma-Delta Modulator Architecture for Mobile Communications

The transition between the second and third generation of mobile communications services can be significantly facilitated by the design of reconfigurable mobile phones. This paper presents an architecture for dual standard receptors, which uses a reconfigurable sigma delta modulator for digitalization at intermediate frequency or at baseband. The proposed approach has been compared with the existing methods. High level simulations show its feasibility.

E. Allier, G. Sicard, L. Fesquet, M. Renaudin
Asynchronous ADCs: Design Methodology and Case Study

We present a new class of Analog-to-Digital Converters (ADCs), based on an irregular sampling of the analog signal, and an asynchronous design. Because these ADCs are not conventional, a design methodology is also presented. It determines their characteristics given the required Effective Number of Bits and the properties of the analog signal to convert. A prototype has been designed for speech applications, using the 0.18-µm CMOS technology from STMicroelectronics. Electrical simulations prove that the Figure of Merit (FoM) is increased by more than one order of magnitude compared to synchronous Nyquist ADCs.

Kalle Folkesson, Christer Svensson
An Accurate ADC Model in Radar System Simulation

To show the usefulness of performing system simulations with an accurate ADC model, some simulations of a radar receiver are presented. The accurate model gives very different results than simple characterization with SNR and SFDR. System performance varies quite much for ADCs with the same specified performance in terms of SNR or SFDR depending on which error mechanism is active in the ADC. With this detailed knowledge of how the ADC affects system performance, the ADC requirement margin can be reduced thus saving cost and power consumption.

Jianhua Gan, Shouli Yan, Jacob Abraham
Novel Calibration Method for a 16-bit 1.5 Megasamples/s Successive Approximation ADC with Non-binary Capacitor Array

A novel calibration method for successive approximation analog-to-digital converter with non-binary capacitor array is presented. It takes advantage of the redundancy in the radix less than 2 non-binary capacitor array and the adaptive calibration algorithm. The capacitor weights are adaptively calibrated to accurately reflect the actual capacitance ratios in the fabricated capacitor array even without good capacitor matching. The capacitor weights are calibrated to better than 22-bit accuracy. The matching requirement in the capacitor array is greatly relaxed. The method is used to design a 16-bit, 1.5 megasamples/s successive approximation analog-to-digital converter.

Takamoto Watanabe, Mitsuo Nakamura, Sumio Masuda
An all-digital A/D converter for fast conversion with 4-TAD parallel construction using moving-average filtering

An all-digital A/D converter (ADC) for fast conversion with 4-TAD [1] parallel construction is presented. The basic structure of the TAD is a completely digital circuit including a ring-delay-line (RDL) with delay units (DUs), along with a frequency counter, latch and encoder. The operating principles are, firstly, that the delay time of the DU is modulated by the A/D conversion voltage (Vin); and secondly, that the delay pulse passes through a number of DUs within a sampling (= integration) time, and the number of DUs through which the delay pulse passes is output as conversion data. The single-TAD area is 0.29 mm² (0.65-µm CMOS) with a resolution of 1 mV/LSB (1 MS/s). Also, its non-linearity is ±1% FS per 1000 mV span (1.5-2.5 V). This non-linearity error can be easily compensated for by digital processing using reference points, resulting in FS of less than ±0.1%. A resolution of 12 mV/LSB (40 MS/s) was realized with 4-parallel TAD. Sample holds are unnecessary, and a low-pass filter function [1] removes high-frequency noise simultaneously with A/D conversion. Thus, the combination of this ADC and the digital filter that follows can eliminate the need for an analog pre-filter. Moreover, this ADC can be easily downsized as process technology advances.

Erland Wikborg
A/D converter in superconductor-semiconductor hybrid technology

Josephson junctions can act as fundamentally accurate voltage-to-frequency converters, and niobium-based superconductor A/D converters (ADCs) have therefore been show-cases for superconductor electronics. But the need for cooling to liquid helium temperature (of 4K) has so far precluded any commercial applications.
In the European project SUPER-ADC (IST 2001- 33468) an alternative "high-temperature" superconductor approach is being pursued: a hybrid ADC, in which a high-Tc superconductor delta- sigma modulator is interfaced with a CMOS decimation filter. This approach takes advantage of the very high over-sampling rate and fundamental exactness of a high-Tc super-conductor delta-sigma modulator, and the outstanding capability of CMOS technology for complex filtering. The "penalty" is an interface, which has to bridge a (mV-to-V) voltage and a (20 GHz-to-1 GHz) speed mismatch, besides a 30K to room-temperature difference.
This presentation describes, briefly, the underlying surprisingly simple superconductor "rapid single flux quantum" (RSFQ) technology, and some of the details of the hybrid ADC realization.

S. Bernard, F. Azaïs, M. Comte, Y. Bertrand, M. Renovell
Automatic Generation of LH-BIST Architecture for ADC Testing

No generic BIST architecture exists for Analog-to-Digital Converters testing. For each application and test setup we thus have to build a dedicated BIST architecture. In this paper, we show that the LH-BIST architectures based on the Linear Histogram-based test technique are configurable and we evaluate hardware resources according to any given application. We also propose a software tool allowing the automatic generation of the LH-BIST description.

C. Donciu, S. Rapuano
A REMOTE INTER-UNIVERSITY SYSTEM FOR MEASUREMENT TEACHING

In the present paper, the prototype architecture of a geographically distributed educational system oriented to electronic measurement teaching is illustrated. It is based on two measurement laboratories, whose instrumentation will be remotely available. In order to access the instrumentation, the students are required to use only a commercial Internet Web browser. In this way, a complete educational proposal can be economically offered by more laboratories specialized in different measuring fields, located in different countries. At now, the core of the system has been developed within an international research agreement between the Technical University Gh. Asachi, Iasi, Romania, and the University of Sannio, Benevento, Italy.

Page 216 of 977 Results 2151 - 2160 of 9762