The paper examines a behavioral model of sigma-delta analog-to-digital converters (SDADC) which allows the uncertainty of A/D conversion to be evaluated. The most sources of the uncertainty are represented in data sheets of modern SDADC. However, information given by manufacturers now is not enough to evaluate the conversion uncertainty with given probability. The most critical situation takes place for noise of SDADC − the major source of the uncertainty in many cases. This problem is mainly discussed in the paper. Conditions for evaluation of the conversion uncertainty with given probability are found from theoretical analysis, simulation of a typical SDADC electronic model and experimental data. Some propositions for including corresponding parameters and tests into standards are made.

A switched-capacitor bandpass analog-to-digital-converter is one of the circuit blocks used in wireless communication systems to digitize the re- ceived analog signal at certain center frequency (f_c). This particular con- verter is used especially for digital FM or AM radio applications and most of the portable communication devices such as cellular-phones. The main block of this converter is the resonator, which resonates at this f_c center frequency. Two of the main design criteria of the resonators are; to have very high quality resonance peak and to locate the center frequency ac- curately without any shift. However, because of the circuit imperfections, the resonance peak gain and the center frequency have degraded in the previous well-known architectures, seriously.

The analog to digital converter is one of the key devices for future receiver design taking into account performance and cost. Is this dream for true software radio applications ( within certain conditions) achievable in a few years ?
Developing such application will mean very high analog input intermediate frequency with wide bandwidth to be converted with very low spurious intermodulation (much better than – 85 db) translating to 12..14 bit resolution ADC sampled at very high clock rates.
Modeling of such a specification gives special restriction on the choice of the ADC architecture and process. It can be proven that the only architecture suitable for this future radio application is a massive parallel structure. Introducing such a high linearity ADC without any feedback loop needs new parallel DC and AC linearisation in the analog core to correct mismatching.
The choice of the process to use is an other key: CMOS, Bipolar, BiCmos processes have been studied. Taking into account high frequency clock and analog inputs, high resolution, low noise and low power, only BCMOS of Bipolar (with Vpnp) featuring a high Ft and good matching of components are good candidates.
Several ADC have been realized or simulated : starting from 10 bits 1 Gsps or 2 Gsps to 14 bits 200 MSPS with Bicmos or Bipolar process with an Ft of 25 or 75 GHz (SiGe).

In this paper a novel method for the on-line calibration of the DAC used in multi-bit sigma-delta modulators is described. The proposed solution uses an additional trans- mission zero in the noise transfer function located at half of the sampling frequency. The mismatch between each unity element and a reference is properly modulated and located at the notch position. Since the notch frequency is noise free a simple digital processing allows us to measure mismatches and to store them in a digital memory for digital calibration purposes. The paper shows how to practically implement the above-described approach and discusses a convenient method to attain digital correction. Simulation results verify the proposed technique.

In this paper a new structure for a band-pass sigma delta modulator is proposed. The center frequency of the modulator can be tuned in the range between DC to half the sampling frequency by means of only one parameter. The modulator stability and the nearly constant resolution for the whole frequency range are demonstrated.