Phase Noise Measurement of ASIC Voltage Controlled Oscillator and PLL Circuit ADF4002 |
|---|
| Patrik Jurík, Miroslav Sokol, Pavol Galajda |
- Abstract:
- This article describes phase noise measurement of a designed ASIC voltage-controlled oscillator in 0.25 µm SiGe BiCMOS technology, with frequency synthesizer ADF4002 from Analog Devices. The oscillator topology utilized in this design is based on a crosscoupled-transistor configuration, and it incorporates two options for frequency control: varicap and capacitor bank. The oscillator frequency is 11.13 GHz with an adjustment frequency range around ±250 MHz. Phase noise measurements were performed on a custom evaluation board. Oscillator with PLL achieves phase noise λ(100 kHz)= -70 dBc at fc = 11.1353 GHz. The article contains phase noise measurement of ASIC comparisons based on selected parameters, dividers and ADF4002 settings. Comparison with the commercial oscillator TGV2566SM and PLL ADF4002 is introduces as well. Details of the measurement setup and different filter parameters are discussed.
- Keywords:
- Phase Noise Measurement, ASIC Voltage Controlled Oscillator, PLL Circuit ADF4002
- Download:
- IMEKO-TC4-2023-46.pdf
- DOI:
- 10.21014/tc4-2023.46
- Event details
- IMEKO TC:
- TC4
- Event name:
- TC4 Symposium 2023
- Title:
26th IMEKO TC4 Symposium and 24th International Workshop on ADC and DAC Modelling and Testing (IWADC)
- Place:
- Pordenone, ITALY
- Time:
- 20 September 2023 - 21 September 2023