Custom Synthesizable VHDL Processor for Embedded Capacitive Angle Sensor Data Processing |
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| Milos Drutarovsky, Ondrej Benedik, Miroslav Sokol, Pavol Galajda, Jan Saliga, Jan Ligus, Cristian D Stratyinski |
- Abstract:
- We describe custom architecture of a small synthesizable soft processor for the next generation of proprietary capacitive angle sensor (CAPSE) developed by CTRL company for space applications. We process data streams from ADCs by custom developed 16-bit processor. The processor is written in platform independent VHDL code. It uses a small Leros (soft processor) control unit and several custom coprocessors including CORDIC, fixed-point fractional multiplier, and adder with barrel shifter optimized for fractional fixed-point arithmetic. We describe architecture of the proposed processor and present the results of developed custom processor mapping to the target FPGA circuit. The complete processor occupies only ∼2100 Logic Elements in target FPGA and complete firmware has less than 220 instructions. For a 10 kHz sampling rate, it requires less than 3 MHz system clock frequency.
- Keywords:
- Synthesizable VHDL, Embedded Capacitive Angle Sensor, Data Processing
- Download:
- IMEKO-TC4-2023-25.pdf
- DOI:
- 10.21014/tc4-2023.25
- Event details
- IMEKO TC:
- TC4
- Event name:
- TC4 Symposium 2023
- Title:
26th IMEKO TC4 Symposium and 24th International Workshop on ADC and DAC Modelling and Testing (IWADC)
- Place:
- Pordenone, ITALY
- Time:
- 20 September 2023 - 21 September 2023