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A. Stoian, T. Kuberczyk, G. Schultes
A new type of force sensor

A new type of force sensor is proposed, mainly based on standard machine parts. The sensor is made of two spring discs, positioned in mirror one to another and joined together by means of electron beam welding. A sensitive element in shape of a rectangle for example is placed between the spring discs. To design the sensor geometry finite element analysis (FEA) was applied to simulate the mechanical strains and stresses in the force sensor and to improve the sensor characteristics by placing the strain gauges on the maximum strain positions. Calibration tests were performed using a testing machine with dead loads to evaluate the linearity, hysteresis and creep.

Jorge M.E. Saffar, Claudio A. Koch, Eunice M. Ferreira Marques, Renata W. Rocha, Rafael S. Oliveira, Ademir R. Chagas, Rodrigo F. Guilherme
Qualification of force standard machines

The 5.2 kN (id. Mgl) and the 50 kN (id. Mnz) force standard dead-weight machines of the Isaac Newton Laboratory of CETEC, Minas Gerais, Brazil, underwent a process of requalification by INMETRO. The process was based on an inter-comparison programme in which the reference values were generated by the 100 kN dead-weight / 1 MN lever amplification machine of INMETRO Force Laboratory – LAFOR. The 5.2 kN machine was verified for compressive forces of 2 and 5 kN, and the 50 kN machine was verified for 2, 5, 20, and 50 kN compressive forces. Calibration activities were carried out in November, 2006 and in August, 2007. Relative deviations and estimated best measurement capabilities are within the expected range for machines of the type. Considered the eight-year time span since the first qualification programme, the Laboratory has significantly improved its best capability values and the relative deviation of the forces it realises.

Aldo Baccigalupi, Mauro D’Arco
AN EXPERIMENTAL STUDY AIMED AT ANALYSING HORIZONTAL QUANTIZATION AND TIME-BASE JITTER EFFECTS IN WAVEFORMS GENERATED BY MEANS OF DACS

This work analyzes the imperfections that characterize waveforms generated by means of DACs. The attention is mainly paid to horizontal quantization, which is due to the discrete nature of the waveform to be played. Also the effects of time-base jitter, which occur in DAC functioning, are investigated when combined to horizontal quantization. Further remarks are related to other minor effects such as those caused by vertical quantization, which is due to the limited resolution of any DAC

Nejmeddine Jouida, Chiheb Rebai, Adel Ghazel, Dominique Dallet
VHDL-AMS MODELLING OF CONTINUOUS-TIME COMPLEX BANDPASS DELTA SIGMA MODULATOR

Continuous-Time delta sigma modulators (CT ΔΣM), by their nature, are mixed-signal systems. That fact creates a discontinuity in the traditional IC design flow which assumes that “discrete” and “continuous” time domain designs require separate design tools. In this work, we present a top level behavioral approach of modeling CT complex Bandpass (CBP) ΔΣM using VHDL-AMS language. The CT ΔΣ model can be used within the analog IC design environment. Fifth-order CT CBP ΔΣM which is tailor made for Bluetooth and WiFi Low-IF receiver demonstrates clearly the modeling technique.

Petr Suchanek, Vladimir Haasz
APPROACHES TO THE ADC TRANSFER FUNCTION MODELLING

It is necessary to keep at the disposition test signals with a high spectral purity for series measuring e.g. in the area of metrology or electronics. Commercial signal generators do not satisfy higher requirements in this area. Our contribution describes chances of the improvement of their quality while using of suitable filters. There is described the construction of a special generator with a high spectral purity of a signal.

Roberto Lojacono, Arianna Mencattini, Marcello Salmeri, Silvia Sangiovanni
REFERENCE FOLDING SUBRANGING CALIPER ADC

The paper presents a reduced ADC architecture obtained by introducing the subranging technique into the scheme of a caliper AD converter. This last converter was already proposed as an application of a theory which describes the comparison between scales having the steps prime each other. This converter architecture drastically reduces the number of the required resistors for a full flash realization. The introduction of the subranging technique into the caliper ADC here presented reduces also the number of the required comparators. The result is a very compact architecture. The paper describes a first intention architecture based on ideal components. An example of SPICE simulation is given.

A. Mariano, D. Dallet, Y. Deval, J-B. Bégueret
VHDL-AMS BEHAVIOURAL MODELLING OF HIGH-SPEED CONTINUOUS-TIME DELTA-SIGMA MODULATOR

An advanced design methodology using a combination of behavioral models and transistor level models is presented in this paper. This methodology is very interesting for complex mixed-signal IC design, reducing the simulation time and improving the design flexibility. In order to validate the methodology proposed, a High-Speed Bandpass Continuous-Time Delta-Sigma Modulator is modeled. This modulator samples at high-IF signals, performing the direct conversion in the modern RF frontend receivers.

Cristian Zet, Catalin Damian, Cristian Fosalau
NEW TYPE ADC USING PWM INTERMEDIARY CONVERSION

The paper presents a new ADC type that uses an intermediary conversion in PWM signal. The signal is compared with a triangular wave. The pulse width at comparator’s output results proportional with the input voltage. Using a simple counter or a frequency-meter like circuit, it is converted into digital words. This is not a very fast converter (up to 10kS/s) but it is easy to build and it asks reduced costs to expand to multiple simultaneous sampling. This design is aimed for FPGAs, having outside it just a comparator per channel. Hardware signal processing is available immediately in the FPGA. Resolution and accuracy can go as far as 12, 14 or 16 bits. The converter presented in the following is 12 bits resolution and measure voltages from -2 V to 2 V. Static errors are also presented.

N. Björsell, M. Isaksson, P. Händel, D. Rönnow
KAUTZ-VOLTERRA MODELLING OF AN ANALOGUE-TO-DIGITAL CONVERTER USING A STEPPED THREE-TONE EXCITATION

In many test and measurement applications, the analogue-to-digital converter (ADC) is the limiting component. Using post-correction methods can improve the performance of the component as well as the over all measurement system. In this paper an ADC is characterised by a Kautz-Volterra (KV) model, which utilises a model-based post-correction of the ADC with general properties and a reasonable number of parameters. Results that are based on measurements on a high-speed 12-bit ADC, shows good results for a third order model.

Attilio Di Nisio, Laura Fabbiano, Nicola Giaquinto, Mario Savino
STATISTICAL PROPERTIES OF AN ML ESTIMATOR FOR STATIC ADC TESTING

A maximum likelihood estimator is derived for the problem of measuring the code transition levels of an ADC. The proposed method is intended to characterize the ADC in the static regime, using only constant test signals, except for a small amount of additive noise. The measurement data are employed in a nearly optimal manner, due to the statistical properties of the maximum likelihood estimator, which are thoroughly examined. The reported analysis allows the design of the test under a given uncertainty constraint.

Page 871 of 977 Results 8701 - 8710 of 9762