NONIDEALITIES STUDY OF A CONTINUOUS-TIME DELTA-SIGMA MODULATOR USING VHDL-AMS MODELLING |
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| A. Mariano, D. Dallet, Y. Deval, J-B. Bégueret |
- Abstract:
- In this paper, a complete high-speed Continuous-Time Bandpass Delta-Sigma modulator for digital receiver applications is modeled, using VHDL-AMS. The main Continuous-Time Delta-Sigma modulator’s nonidealities such as excess loop delay, clock jitter and multi-bit feedback DAC element mismatch in the modulator loop are also modeled and their effects evaluated. An accurate understanding of these non-ideal phenomena allows to estimate the limits of the modulator and hence to design more robust building-blocks.
- Download:
- IMEKO-IWADC-2008-038.pdf
- DOI:
- -
- Event details
- IMEKO TC:
- TC4
- Event name:
- IWADC 2008
- Title:
13th IMEKO TC4 Workshop on ADC Modelling and Testing IWADC (together with XVIth IMEKO TC4 International Symposium on Electrical Measurements and Instrumentation) (IWADC)
- Place:
- Florence, ITALY
- Time:
- 22 September 2008 - 24 September 2008